With today's software being developed, computer systems are in need of larger memory systems in order to adequately and efficiently run such software programs. As a result, memory systems often occupy a large amount of the integrated circuit ("chip") area. Often such memory cell arrays operate as cache memories associated with the microprocessor. As these memory arrays grow larger (even if the area occupied by the memory array does not increase, the number of transistors needed to implement the array may still increase) it is necessary to ensure that the performance of the array improves, or at least does not degrade.
With such memory arrays, memory latency is a critical performance limiter. Means to speed up memory access for memory array designs are needed for memory chips and embedded memories. This is more critical as larger DRAMs are embedded on microprocessor chips as large caches or system memory. Therefore, there is a need in the art for increasing the speed of the transition time for memory accesses in memory arrays.